FIR Filter Design Using The Signed-Digit Number System and Carry Save Adders – A Comparison
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چکیده
This work looks at optimizing finite impulse response (FIR) filters from an arithmetic perspective. Since the main two arithmetic operations in the convolution equations are addition and multiplication, they are the targets of the optimization. Therefore, considering carry-propagate-free addition techniques should enhance the addition operation of the filter. The signed-digit number system is utilized to speedup addition in the filter. An alternative carry propagate free fast adder, carry-save adder, is also used here to compare its performance to the signed-digit adder. For multiplication, Booth encoding is used to reduce the number of partial products. The two filters are modeled in VHDL, synthesized and place-androuted. The filters are deployed on a development board to filter digital images. The resultant hardware is analyzed for speed and logic utilization Keywords— FIR Filters – Signed Digit – Carry-Save – FPGA
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تاریخ انتشار 2014